1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to conductive structures, such as copper-based metallization layers, comprising wide metal lines connected to closely spaced narrow metal lines.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, a plurality of stacked “wiring” layers, also referred to as metallization layers, is usually provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures despite the provision of a relatively large number of metallization layers owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, a material with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers. In order to provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less than desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed so as to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine and the like, into the copper. Furthermore, the conductive barrier layers may also provide highly stable interfaces with the copper, thereby reducing the probability for significant material transport at the interface, which is typically a critical region in view of increased diffusion paths that may facilitate current induced material diffusion. Currently, tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices, the void free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the basic geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure so as to insure both high yield and the required product reliability.
In addition to achieving high production yield and superior reliability of the metallization system, it is also important to achieve a high level in production yield and reliability on the basis of a high overall throughput of the manufacturing process under consideration. For instance, the so-called dual damascene process is frequently used in which a via opening and a corresponding trench are filled in a common deposition sequence, thereby providing superior process efficiency.
In the damascene technique or inlaid technique, typically the patterning of the via opening and the trenches may require sophisticated lithography techniques since the shrinkage of critical dimensions in the device layer, i.e., for transistors and other semiconductor circuit elements, may also require a corresponding adaptation of the critical dimensions of the vias and metal lines to be formed in the metallization system. In some well-established process techniques, a patterning regime may be used, which may commonly be referred to as “via first/trench last” approach in which at least a portion of a via opening may be formed first on the basis of a specific etch mask and thereafter a corresponding trench mask may be provided in order to form a corresponding trench in the upper portion of the dielectric material, wherein, depending on the overall process strategy, during the trench etch process, the remaining portion of the via opening may also be completed, while, in other cases, the via opening may be provided such that it extends down to a bottom etch stop layer, which may then be opened after completing the trench etch process. Consequently, a complex patterning regime including at least two lithography steps may have to be used in which at least the lithography process for defining the lateral size of the via openings represents a highly critical process step, since the via openings may typically have critical dimensions in both lateral directions, requiring extremely sophisticated lithography tools and related process techniques. With shrinking critical dimensions, however, a precise definition of the lateral size of the via opening may become increasingly difficult, since, for instance, the thickness of sophisticated resist materials may have to be adapted to the reduced wavelength of sophisticated lithography tools, which may on the other hand restrict the etch resistivity of the resist mask. Furthermore, additional process steps may be required for planarizing the overall surface topography for forming the trench mask after etching at least a portion of the via opening into the dielectric material of the metallization layer under consideration. Consequently, many advantages in view of process efficiency of a dual damascene technique may be offset or even over-compensated for by the requirement for the very complex patterning regime, wherein, in particular, the precise definition of a required reduced target size of the via openings may necessitate extremely difficult and thus failure-prone lithography steps.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.